1. Field of the Invention
This invention relates to output drive circuits, and more particularly to such circuits which are fabricated with a CMOS process and use field effect transistors characterized by associated parasitic bipolar transistors.
2. Description of the Prior Art
It is desirable that an output drive circuit have a very high input impedance and a low output impedance. It is also desirable that the circuit be characterized by a high "swing", which is a measure of how close the output voltage comes to the voltage level at the positive supply bus.
FIG. 1 shows a basic type of prior art output drive circuit implemented with a field effect transistor (FET) formed with a CMOS (complementary metal oxide semiconductor) process. The FET 2 includes a gate 4 that is connected to an input voltage terminal 6, a drain 8 connected to a positive voltage bus 10, and a source 12 and back-gate 14 connected in common to an output voltage terminal 16. A current source 18 draws current from the common source/back-gate connection and delivers current to a negative voltage bus or ground terminal 20. As shown, FET 2 is an n-channel output follower, with the back-gate 14 provided by a p-well on an n-type substrate. The circuit has the advantage of an almost infinite input impedance, but it also has a relatively high output impedance. The high output impedance is a distince disadvantage when driving relatively heavy loads at the output terminal.
Another type of prior art output drive circuit is shown in FIG. 2. This circuit consists of an npn bipolar transistor 22 having its base connected to an input voltage terminal 24, its collector connected to a positive voltage bus 26, and its emitter connected to an output load terminal 28. A current source 30 draws current from the emitter to a negative voltage bus or ground terminal 32.
The circuit of FIG. 2, known as an emitter follower, is characterized by a relatively low input impedance approximately equal to the product of the transistor current gain multiplied by the load resistance. Its input impedance can be increased by a factor approximately equal to the transistor current gain by means of a "Darlington" connection illustrated in FIG. 3. In this circuit a second bipolar transistor 34 has its base connected to the emitter of the first transistor 22, its collector connected in common with the collector of the first transistor, and a current source 36 drawing current from its emitter to the negative voltage bus or ground terminal 32. The output load terminal 28 is connected to the emitter of the second transistor 34. Unfortunately, even the improved input impedance offered by the Darlington circuit is too low for many applications.
Another approach that can be taken to provide an output drive circuit with high input impedance but low output impedance involves a standard p-well CMOS process to fabricate the circuit devices. It is known that, under certain conditions, an FET fabricated with a CMOS process can operate in a manner similar to a bipolar transistor; the device is described as having a "parasitic" bipolar transistor. This penomenon is illustrated in FIG. 4. The FET illustrated is fabricated on an n-type substrate 40 which is maintained at the voltage level of a positive voltage bus. A well 42 of p-type material is set into the substrate, with the FET formed in the well. Two n+ regions are diffused into the well, the first n+ implant 44 comprising the FET source and the other n+ implant 46 comprising its drain. Between the two n+ implants the surface of the well is oxidized to form an insulator strip 48, typically SiO.sub.2 about 1,000-2,000 angstroms thick. A gate electrode 50 is then deposited on the insulator strip. If the p-well is heavily doped a surface inversion layer will normally not be present, and the FET will be off since there will be only a small leakage current between the source and drain. When a positive voltage is applied to the gate, a negative charge concentration is induced under the oxide layer 48 on the surface of the well. This induced negative charge consists of a combination of ionized acceptor impurities and free elecrons, producing a surface layer on the well which is now n-type. Such a layer on a p-type material is referred to as an inversion layer. When this induced n-type layer bridges the space between the source and drain implants, it forms a conducting channel containing free electrons. In the operation of the FET the p-well functions as its back-gate.
A parasitic bipolar transistor 52 associated with the described FET is shown in dashed lines. It can be seen that, in travelling down from the n+ source implant 44 through the P-well 42 to the N-substrate 40, an npn section is traversed. Under appropriate conditions these elements function as an npn bipolar transistor. The transistor's emitter is formed by the n+ source implant 44, its base by the p-well 42 (accessed through a p+ implant 54), and its collector by the n-substrate 40 which is maintained at V+.
A circuit has previously been devised which makes use of this parasitic bipolar transistor to achieve an output drive circuit with high input and low output impedances. This circuit, shown in FIG. 5, includes an FET which is similar to that shown in FIG. 1 and labeled with corresponding reference numerals. The back-gate 14 (p-well) is connected to the FET's source 12 to prevent the associated parasitic bipolar transistor from turning on and conducting; the back-gate can also be connected to the V- voltage bus for the same purpose. The FET source 12 is connected to the base of a separate bipolar transistor 56 which has its collector connected to V+ terminal 10 and its emitter connected to the circuit's output terminal 58. A second current source 59 draws current through the emitter to the V- or ground terminal 20. This circuit has been found to have both the high input impedance of the FIG. 1 circuit and the low output impedance of the FIG. 3 circuit. However, even in a best case implementation, its output voltage swing is limited in the positive direction to the sum of an NMOS FET threshold voltage (V.sub. T) and a bipolar base-emitter voltage (V.sub.BE) from the V+ supply voltage. This swing is worse than that exhibited by either the FIG. 1 or FIG. 3 circuits, and makes the circuit unsuitable for certain applications.